TITLE: An FPGA implementation of an Iterative Decoder based on Low Density Parity Check codes

WHEN: December 5, 2003, 3:00-5:00 PM

WHERE: IS Bldg., 1st floor Conference Room

WHO: Gayatri Mehta

Committee:

Dr. Prashant Krishnamurthy,
Dr. Richard Thompson
Dr. Heung-no Lee

ABSTRACT: Low Density Parity Check codes were invented in 1962 by Gallager and during the past several years, the research on these error correcting codes has been exciting, motivated by their near Shannon-limit performance and simplicity in decoding algorithm. The aim of this research is to develop a hardware prototype model of an Iterative Decoder based on low density parity check codes (LDPCC). This research mainly concentrates on the simulation study of the encoding and decoding algorithms of LDPC codes, the study and proposal of efficient VLSI architectures for LDPCC Decoder that can provide low complexity and fast decoding solutions, and the implementation of the decoder on an FPGA chip. The implementation of a fully parallel LDPCC decoder on Xilinx Virtex-II chip is described by taking examples of (4,8) 16-bit LDPCC decoder and (4,8) 2048-bit LDPCC decoder. A fully parallel LDPCC decoder architecture leads to an increase in the hardware complexity and a routing overhead to a significant amount which makes it an unattractive option for many real applications. In order to circumvent these limitations, a partly parallel architecture is designed. This design starts with our own method of generating the parity check matrix which results in the partly parallel architecture of the decoder. The architecture may be utilized in a decoder which supports multiple block lengths. We describe the hierarchical design and the implementation of the decoder in detail with an example of (4,8) 2048-bit decoder on Xilinx Virtex-II chip. The (4,8) 2048-bit LDPCC decoder so designed achieves a throughput of 33 Mbps.